(1) Field of the Invention
The invention relates to a negative resistance diode device for high frequency RF applications, and more particularly, to a gate-controlled, negative resistance diode device that utilizes band-to-band tunneling.
(2) Description of the Prior Art
As CMOS technology continues to reduce in device scale, the operating frequency of these circuits increases. For example, the digital signals in state-of-the art microprocessors are operating in excess of about 500 MHz clock frequency and will approach about 1 GHz very soon. Further, the small signal operating frequency of CMOS transistors, fabricated at feature sizes of about 0.25 microns, is in the range of about 1 GHz for radio frequency (RF) wireless applications.
Typical on-chip clock generator circuits are presently based on ring oscillator designs wherein a series of inverters are connected in a ring. The operating frequency of such ring oscillators is determined by the total propagation delay from the first inverter to the last inverter. Often, these ring oscillator circuits consume a large chip area because many inverters must be placed in series. In addition, a large switching noise is generated by these ring oscillator designs.
As an alternative to CMOS inverters, devices that are called xe2x80x9cnegative resistancexe2x80x9d diodes are known in the art. For example, impact ionization avalanche transit time (IMPATT) diodes and barrier injection transit time (BARITT) diodes may be used to create negative resistance diode functions. IMPATT and BARITT diodes have been found to be useful in the formation of oscillators and amplifiers for high frequency RF and microwave applications. However, as will be shown in the following observations, these prior art devices have several disadvantages.
Referring now to FIG. 1, a simplified diagram of an IMPATT diode device is shown. Further, a graph of the electric field distribution across this IMPATT device during normal operation is illustrated. The IMPATT device comprises semiconductor bulk regions 14, 18, 22, and 26. This semiconductor bulk region further comprises a source region 14, a barrier region 18, a drift region 22, and a collector region 26. A typical dopant profile is shown in the illustration. The source region 14 is heavily doped n-type (n+). The barrier junction 18 is doped p-type (p). The drift region 22 is very lightly doped, or nearly intrinsic, and may be either n-type ("igr") or p-type (xcexd). The collector region 26 is heavily doped p-type (p+).
The operating principle of the IMPATT diode is based on two effects: the generation of charge carriers via impact ionization and the finite transit time of such charge carriers in a depleted drift region. The IMPATT diode requires a dc bias voltage VDC 30. The dc bias voltage VDC 30 creates a reverse bias across the source-to-barrier (n+/p) junction 14 and 18. This dc bias voltage VDC 30 is preferably high enough to deplete the drift region 22 and to be near the onset of reverse avalanche current. An ac voltage signal VAC 34 is placed across the IMPATT diode device in series with the dc bias voltage VDC 30. As can be seen from the graph, the static electric field caused by the dc bias voltage VDC 30 is spread across the barrier junction 18 and the drift region 22.
Referring now to FIG. 2, the high frequency operation of the IMPATT device is shown. The ac voltage signal VAC 34 is plotted 60 as a frequency multiple of time (xcfx89t). During a positive cycle, between 0 and xcfx80, the magnitude of the ac voltage signal VAC 34 is large enough to trigger significant impact ionization occurs at the source-to-barrier interface 14 and 18. Electron-hole pairs are thereby generated and, later, multiplied by the avalanche mechanism. Holes are collected toward the barrier region (p) side 18 while the electrons are collected in the source region (n+) side 14.
Due to the nature of avalanche multiplication, the maximum magnitude of the hole current, Io(t) 64, occurs at the end of the positive cycle of the ac voltage signal VAC 34, or at the time xcfx80. Therefore, the maximum hole current Io(t) 64 generated in the source-to-barrier interface 14 and 18 exhibits a xcfx80/2 delay from the maximum ac voltage, which is typically known as the xe2x80x9cxcfx80/2 avalanche delay.xe2x80x9d
Once the holes enter the drift region 22, the carrier transport mechanism comprises carrier drift because the drift region 22 is nearly intrinsic and is depleted. The external current flow Ie(t) 68 begins just as the ac voltage signal VAC enters the negative cycle between xcfx80 and 2xcfx80. If the drift region 22 is long enough such that the transit time or drift time is exactly xcfx80 (wherein xcfx80=xcfx89L/vs), then the external current Ie(t) is 180 degrees out of phase with the ac voltage signal. In other words, a small-signal xe2x80x9cnegative resistancexe2x80x9d has been achieved. This negative resistance actually delivers power to the external circuit from the diode device. Such a device may be used for the creation of an oscillator circuit, for example.
Referring now to FIG. 3, a BARITT diode device is illustrated in simplified form. An electric field distribution plot is given. A semiconductor bulk layer comprises a source region 108, a graded barrier region 112 and 116, a drift region 120, and a collector 124. The source junction 108 is heavily doped p-type (p+). The graded barrier region 112 and 116 comprises a moderately doped n-type region (n1) 112 and a heavily doped n-type region (n+) 116. The drift region 120 comprises a lightly doped, or nearly intrinsic, region of semiconductor that is lightly doped n-type (n2). The collector region 124 is heavily doped p-type (p+).
The operating principle of the BARITT diode is based on two effects: the generation of charge carriers via barrier injection of a forward biased p-n diode and the finite transit time of such charge carriers in a depleted drift region. The BARITT diode requires a dc bias voltage VDC 128. The dc bias voltage VDC 128 creates a forward bias of, for example, about 0.7 V across the source-to-barrier (p+/n1) junction 108 and 116. This dc bias voltage VDC 30 is preferably high enough to deplete the drift region 120. An ac voltage signal VAC 132 is placed across the BARITT diode device in series with the dc bias voltage VDC 128. The static electric field caused by the dc bias voltage VDC 128 causes the drift region (n2) 120 to be fully depleted. The electric field is distributed 130 across the BARITT device as shown.
Referring now to FIG. 4, the high frequency operation of the IMPATT device is shown. The ac voltage signal VAC 132 is plotted 150 as a frequency multiple of time (xcfx89t). During a positive cycle, between 0 and xcfx80, the p+/n1 is forward biased. Significant hole current, Io(t) 160, is injected into the n1 region 112. Note that, the much lower doping of the n1 region 112 compared to the p+ junction 116 means that the corresponding electron injection current from the n1 region 112 to the p+ region 108 is negligible when compared to the magnitude of the hole current Io(t) 160. Holes are collected toward the heavily doped portion of the barrier junction (n+) 116.
Due to the nature of a forward biased p-n junction, the maximum magnitude of the hole current, Io(t) 160, occurs at the midpoint of the positive cycle of the ac voltage signal VAC 132, or at the time xcfx80/2. Therefore, the maximum hole current Io(t) 160 generated exhibits no xcfx80/2 delay from the maximum ac voltage and is therefore xe2x80x9cin phasexe2x80x9d with the ac voltage.
Once the holes enter the drift region (n2) 120, the carrier transport mechanism comprises carrier drift because the drift region 120 is nearly intrinsic and is depleted. The external current flow Ie(t) 164 begins just as the ac voltage signal VAC 132 hits midpoint of the positive cycle between 0 and xcfx80. The external current flow Ie(t) 164 continues during the negative half-cycle of the ac voltage signal VAC 132 due to the drift region 120 finite transit time. If the drift region 120 is long enough such that the transit time or drift time is exactly 3xcfx80/2 (wherein xcfx80=xcfx89L/vs), then the external current Ie(t) is 180 degrees out of phase with the input ac voltage 132 during the negative half-cycle from xcfx80 to 2xcfx80. Once again, a small-signal xe2x80x9cnegative resistancexe2x80x9d or power gain has been achieved. However, in this case, a significant amount of power loss is incurred due to the xe2x80x9cpositive resistancexe2x80x9d quarter cycle from xcfx80/2 to xcfx80 of the ac voltage cycle.
It is found, therefore, that the BARITT diode exhibits a lower power conversion efficiency than the IMPATT diode due to the above-mentioned power loss. However, the IMPATT diode suffers from two disadvantages. First, a large dc voltage of, for example, greater than about 30 Volts must be provided not only to deplete the drift region but also to induce the avalanche injection. It is difficult to provide this large voltage in a sub-micron integrated circuit device. Second, the impact ionization and avalanche multiplication process generate a large amount of noise. By comparison, the BARITT device generates less noise and can be operated at a lower dc bias of, for example, about 15 Volts. Unfortunately, the BARITT diode suffers from higher loss and still requires a somewhat large voltage to fully deplete the drift region of carriers. Finally, both the IMPATT and the BARITT devices of the prior art are difficult to integrate in a monolithic VLSI process. Therefore, these devices are typically only available in discrete form.
Several prior art inventions describe high frequency or transit time devices. U.S. Pat. No. 5,675,295 to Brebels et al teaches a microwave oscillator device and a method of manufacture thereof. The oscillator may use any of several resonant tunnel diode (RTD) devices as the active component. The RTD may comprise a BARITT diode. U.S. Pat. No. 4,745,374 to Nishzawa et al discloses a transit time, negative resistance device that performs carrier injection by both avalanche and tunneling. The diode is formed by a GaAs stack comprising p+/n+/nxe2x88x92/n+. U.S. Pat. No. 4,358,759 to Stewart et al teaches the application of a BARITT diode in a microwave movement detector circuit. U.S. Pat. No. 5,617,104 to Das discloses a tunable ferroelectric transmitting system where a negative resistance diode, such as an IMPATT, is used. In the article, xe2x80x9cMonolithic IMPATT Technology,xe2x80x9d by Bayraktaro, in Microwave Journal, April 1989, pp. 73-86, a monolithic IMPATT diode is described. In the article, xe2x80x9cComparison of GIDL in p+-poly PMOS and n+-poly PMOS Devices,xe2x80x9d by Lindert et al, IEEE Electron Device Letters, Vol. 17, No. 6, June 1996, pp.285-287, discusses a related matter concerning gate-induced drain leakage (GIDL) in LDD MOSFETs.
A principal object of the present invention is to provide a negative resistance diode device in the manufacturing of an integrated circuit device.
A further object of the present invention is to provide a negative resistance diode device wherein a gate controls the device operation.
A yet further object of the present invention is to create a gate-controlled, negative resistance diode device that is integrated into a MOS process.
Another yet further object of the present invention is to create a gate-controlled, negative resistance diode device, which exhibits excelled negative resistance (gain) and low loss at high signal frequencies.
Another yet further object of the present invention is to create a gate-controlled, negative resistance diode device that may be used with a relatively small DC bias.
Another further object of the present invention is to provide an effective method of manufacturing a negative resistance diode device.
In accordance with the objects of this invention, a new gate-controlled, negative resistance diode device is achieved. The device comprises, first, a semiconductor layer in a substrate. The semiconductor layer contains an emitter region and a barrier region. The barrier region is in contact with the emitter region and is laterally adjacent to the emitter region. The semiconductor layer contains a collector region. A drift region comprises the semiconductor layer between the barrier region and the collector region. Finally, a a gate comprises a conductor layer overlying the drift region, the barrier region, and at least a part of the emitter region with an insulating layer therebetween.
Also in accordance with the objects of this invention, a new method to form a gate-controlled, negative resistance diode device in the manufacture of an integrated circuit device is achieved. A semiconductor layer is provided in a substrate. Ions are selectively implanted into the semiconductor layer to form an emitter region. Ions are implanted into the semiconductor layer to form a barrier region. An insulator layer is formed overlying the semiconductor layer. A conductor layer is deposited overlying the insulator layer. The conductor layer may be metal or polysilicon and may be ion implanted. The conductor layer is patterned to form a gate. The gate overlies the barrier junction and at least a part of the emitter region. Ions are implanted into the semiconductor layer to form a collector region and to complete the diode device in the manufacture of said integrated circuit device. A drift region is formed in the semiconductor layer where the gate overlies the semiconductor layer between the collector region and the barrier region. The drift region is controlled by applying a bias on the gate region.